Why not: always @(posedge clk) if (core < `CORES_NUM) result[core] = 1;. ... <看更多>

Alternatively ,you can use another case statement. Also you need to control the ou1 range otherwise the upper assigned bits will be out of ... ... <看更多>

Now that we can generate Verilog from code in standard using memories I have ... I wrote test cases that use Vivado that have a loop or talk to memory, ... ... <看更多>